The increasing demand for higher bandwidth in digital communication, instrumentation, sensors, computer peripherals, and other electronic devices and systems continues to drive a corresponding a need for higher speed and higher resolution Analog to Digital Converters (ADCs). A single ADC core circuit implemented in current integrated circuit (IC) technologies cannot meet the conversion requirements of such applications while maintaining low production costs.
An efficient method of providing higher sample rates is to use a parallel combination of slower analog-to-digital converter (ADC) core circuits in a time-interleaved fashion. An M-channel time-interleaved ADC system includes M ADC cores, each operating at a sample rate of 1/M of the overall desired system sample rate. In the absence of any impairments, component or manufacturing variations, or other mismatches among the operating characteristics of the ADC cores, the resulting time-multiplexed output samples are identical to that of a single ideal ADC operating at the system sample rate. In practice, however, there are always mismatches between the different ADCs which can degrade the performance of the ADC system. The commonly occurring mismatches manifest themselves as differences in offset, gain and phase of the ADC cores. In other words, the offsets and gains of all the ADC cores are not the same, and the ADC cores do not all sample at exactly uniform instants of the system sample frequency.